TSMC laid out its production roadmap through 2029 at the North American Technology Symposium last week, and the bullets matter for anyone whose product roadmap depends on bleeding-edge silicon. A13 is scheduled to enter production in 2029, one year after A14, as an incremental optical-shrink enhancement that delivers about 6% area reduction with full design-rule and electrical compatibility to A14. A12 also targets 2029. A16, the 1.6nm node that hyperscaler AI customers had been planning around, has slipped to 2027 production from earlier targets. All four — A16, A14, A13, A12 — use nanosheet transistors, and TSMC explicitly stated that the company does not expect to need High-NA EUV lithography for any of them. That last point is the most strategically loaded one in the entire announcement.
The High-NA EUV detail matters because it is a direct rebuttal to the assumption that ASML's $380M-per-tool High-NA scanners would be the gating technology for sub-2nm production. TSMC is saying it can keep stretching standard EUV — using more multi-patterning passes, better resists, and more aggressive design-technology co-optimization — through 2029 across four full nodes. If that holds, ASML's revenue projection on High-NA shifts meaningfully later, and the customers who already paid the premium for early High-NA access (Intel notably) lose some of the strategic differentiation they were betting on. The competitive subtext is that TSMC is willing to absorb more process complexity rather than depend on a tool stack where ASML has a monopoly and a long lead time. For AI customers buying the chips, the practical effect is the same: production capacity at A14 and A13 will not be limited by High-NA scanner availability, which removes one of the more uncertain bottlenecks from the 2027-2029 supply story.
The A16 slip from late 2026 to 2027 is the part of the announcement that affects current product plans most directly. NVIDIA's Rubin-class architecture, AMD's MI500 series successors, Apple's M5/M6 cycle, and the various hyperscaler-internal AI chips were all in flight assuming an A16 production ramp on the original timeline. A one-year slip pushes the corresponding product launches and the data-center deployments that depend on them. The compute supply curve through 2027 is now likely to be tighter than 2025-era projections assumed, with N2 and N2P doing more of the heavy lifting for longer. Nothing about this changes the demand curve for AI compute, which means cost per training FLOP improves more slowly than the previous roadmap implied, and inference economics at the most demanding model sizes stay closer to current levels through 2027.
For builders, the practical takeaways are operational, not architectural. If your product strategy assumed cheaper AI inference in 2027 because of a node transition, push that timing assumption right by a year. If you were planning to wait for High-NA-enabled chips to start designing efficient agent or inference deployments, you can stop waiting because TSMC just told you those chips are not coming in the timeframe you expected and the alternative is good enough. The interesting product-roadmap question for the next 18 months is what happens at the A14 node when A14 is the latest available process for longer than originally planned — there will be more design-time investment in the same node, which usually means cleaner libraries, better pre-validated IP, and lower foundry risk for second-tier customers. Cheap, abundant N2/N2P/A14 capacity is a friendlier environment to build product roadmaps against than uncertain High-NA pioneer capacity. Plan accordingly.